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CHROMATIC RES INC

Overview
  • Total Patents
    37
About

CHROMATIC RES INC has a total of 37 patent applications. Its first patent ever was published in 1994. It filed its patents most often in United States, Australia and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets computer technology, machines and consumer goods are KANO COMPUTING LTD, XIONG SHILIN and HARDIE-BICK ANTHONY RICHARD.

Patent filings per year

Chart showing CHROMATIC RES INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Purcell Stephen C 15
#2 Wang Avery L 7
#3 Battle James T 5
#4 Smith Wade K 4
#5 Hung Andrew C 3
#6 Farmwald P Michael 3
#7 Fogg Chad E 3
#8 Inman Jennifer F 3
#9 Lum Sanford S 3
#10 Gulsen Denis 3

Latest patents

Publication Filing date Title
US6002410A Reconfigurable texture cache
US5982373A Dynamic enhancement/reduction of graphical image data resolution
US5949439A Computing apparatus and operating method using software queues to improve graphics performance
US5838968A System and method for dynamic resource management across tasks in real-time operating systems
US5719802A Adder circuit incorporating byte boundaries
US5814750A Method for varying the pitch of a musical tone produced through playback of a stored waveform
US5828881A System and method for stack-based processing of multiple real-time audio tasks
US5834672A Non-linear tone generator
US5859787A Arbitrary-ratio sampling rate converter using approximation by segmented polynomial functions
US5727211A System and method for fast context switching between tasks
US5864704A Multimedia processor using variable length instructions with opcode specification of source operand as result of prior instruction
US5812437A Programmable logic unit for arithmetic, logic and equality functions
US5751622A Structure and method for signed multiplication using large multiplier having two embedded signed multipliers
US5799169A Emulated registers
US5664154A M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location's dirty bit indicates a write-back
US5712799A Method and structure for performing motion estimation using reduced precision pixel intensity values
US5586070A Structure and method for embedding two small multipliers in a larger multiplier
US5477543A Structure and method for shifting and reordering a plurality of data bytes
US5625784A Variable length instructions packed in a fixed length double instruction
US5623434A Structure and method of using an arithmetic and logic unit for carry propagation stage of a multiplier