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BULL HN INFORMATION SYST

Overview
  • Total Patents
    737
  • GoodIP Patent Rank
    210,156
About

BULL HN INFORMATION SYST has a total of 737 patent applications. Its first patent ever was published in 1980. It filed its patents most often in United States, EPO (European Patent Office) and Australia. Its main competitors in its focus markets computer technology, machines and digital networks are SCIENCE PARK CORP, KAVURI SRINIVAS and COMMVAULT SYSTEMS INC.

Patent filings per year

Chart showing BULL HN INFORMATION SYSTs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Barlow George J 38
#2 Keeley James W 35
#3 Ryan Charles P 35
#4 Joyce Thomas F 34
#5 Guenthner Russell W 32
#6 Lemay Richard A 29
#7 Shelly William A 27
#8 Egolf David A 27
#9 Lange Ronald E 23
#10 Zulian Ferruccio 23

Latest patents

Publication Filing date Title
US2016191743A1 Method and system for linking, attaching and retrieving video clips on postcards
US2016188351A1 Process for providing increased power on demand in a computer processing system with submodeling
US2016179573A1 Method for providing mainframe style batch job processing on a modern computer system
EP2595057A2 Modified backfill scheduler and a method employing frequency control to reduce peak cluster power requirements
EP2549427A1 Scan my mail postal mail to electronic communication connection
EP2354939A1 Method and apparatus providing cobol decimal type arithmetic functions with improved performance
US2007156390A1 Performance improvement for software emulation of central processor unit utilizing signal handler
US2006165094A1 Encapsulation of large native operating system functions as enhancements of the instruction set in an emulated central processor system
US2006155524A1 Instructions to load and store containing words in a computer system emulator with host word size larger than that of emulated machine
EP1528487A2 Method for improving performance of critical path in field programmable gate arrays
US2006048162A1 Method for implementing a multiprocessor message queue without use of mutex gate objects
US2005246566A1 Process for providing submodel performance in a computer processing unit
US2005071793A1 Formal proof methods for analyzing circuit loading problems under operating conditions
US6973539B2 Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords
US2004193804A1 Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment
US2004111585A1 Associative memory system with a multi-digit incrementable validity counter
US2004111551A1 Emulated target associative memory system with a multi-digit incrementable validity counter
US6868483B2 Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment
US6760811B2 Gateword acquisition in a multiprocessor write-into-cache environment
US2003154423A1 Rebuilding “in-doubt” states reliably after multiple system failures in a data processing system performing two-phase transaction processing