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Managing processor-state transitions
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Power state management of an input/output servicing component of a processor system
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Method and apparatus for thermal control of processing nodes
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Method and apparatus for demand-based control of processing node performance
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Method and apparatus for cache control
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Method and apparatus for memory power management
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Controlling performance/power by frequency control of the responding node
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Method and apparatus for transitioning devices between power states based on activity request frequency
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North-bridge to south-bridge protocol for placing processor in low power state
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Optimization of application power consumption and performance in an integrated system on a chip
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Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state
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Protocol for power state determination and demotion
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Hardware monitoring and decision making for transitioning in and out of low-power state
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