US2014047450A1
|
|
Utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer
|
US2013304948A1
|
|
Managing a direct memory access (‘DMA’) injection first-in-first-out (‘FIFO’) messaging queue in a parallel computer
|
US2012210094A1
|
|
Data communications in a parallel active messaging interface of a parallel computer
|
US2012179736A1
|
|
Completion processing for data communications instructions
|
US2012179760A1
|
|
Completion processing for data communications instructions
|
US2012124249A1
|
|
Method of data communications with reduced latency
|
US2012117281A1
|
|
Fencing direct memory access data transfers in a parallel active messaging interface of a parallel computer
|
US2012117211A1
|
|
Fencing data transfers in a parallel active messaging interface of a parallel computer
|
US2012117138A1
|
|
Fencing network direct memory access data transfers in a parallel active messaging interface of a parallel computer
|
US2012117137A1
|
|
Fencing data transfers in a parallel active messaging interface of a parallel computer
|
US2011258245A1
|
|
Performing a local reduction operation on a parallel computer
|
US2011173287A1
|
|
Preventing messaging queue deadlocks in a DMA environment
|
US2010082848A1
|
|
Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment
|
US2009037707A1
|
|
Determining when a set of compute nodes participating in a barrier operation on a parallel computer are ready to exit the barrier operation
|
US2009031002A1
|
|
Self-pacing direct memory access data transfer operations for compute nodes in a parallel computer
|
US2009019190A1
|
|
Low latency, high bandwidth data communications between compute nodes in a parallel computer
|
US2008313661A1
|
|
Administering an epoch initiated for remote memory access
|
US2008168313A1
|
|
Memory error monitor
|