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BAUMGARTNER JASON R

Overview
  • Total Patents
    37
About

BAUMGARTNER JASON R has a total of 37 patent applications. Its first patent ever was published in 2006. It filed its patents most often in United States. Its main competitors in its focus markets computer technology are NIPPON SYST KAIHATSU KK, AGOSTINI ORGANIZZAZIONE SRL D and JIE BAI.

Patent filings in countries

World map showing BAUMGARTNER JASON Rs patent filings in countries
# Country Total Patents
#1 United States 37

Patent filings per year

Chart showing BAUMGARTNER JASON Rs patent filings per year from 1900 to 2020

Focus industries

# Industry
#1 Computer technology

Focus technologies

Top inventors

# Name Total Patents
#1 Baumgartner Jason R 37
#2 Mony Hari 29
#3 Case Michael L 23
#4 Kanzelman Robert L 22
#5 Paruthi Viresh 11
#6 Janssen Geert 4
#7 Roessler Paul J 3
#8 Bobok Gabor 2
#9 Williams Mark Allen 2
#10 Roessler Paul Joseph 2

Latest patents

Publication Filing date Title
US8578311B1 Method and system for optimal diameter bounding of designs with complex feed-forward components
US2013290918A1 Constructing inductive counterexamples in a multi-algorithm verification framework
US8527922B1 Method and system for optimal counterexample-guided proof-based abstraction
US2012151423A1 Large scale formal analysis by structural preprocessing
US2012272197A1 Enhancing redundancy removal with early merging
US2012271786A1 Efficiently determining boolean satisfiability with lazy constraints
US2012054701A1 Optimal correlated array abstraction
US2012054702A1 Techniques for employing retiming and transient simplification on netlists that include memory arrays
US2011276932A1 Array concatenation in an integrated circuit design
US2011276930A1 Minimizing memory array representations for enhanced synthesis and verification
US2011276931A1 Eliminating, coalescing, or bypassing ports in memory array representations
US2011271244A1 Enhanced analysis of array-based netlists via reparameterization
US2011270597A1 Tracking array data contents across three-valued read and write operations
US2011271242A1 Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays.
US2011271243A1 Enhanced analysis of array-based netlists via phase abstraction
US2011093825A1 Techniques for analysis of logic designs with transient logic
US2011093824A1 Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design
US2011016441A1 Method and system for dynamic automated hint generation for enhanced reachability analysis
US2010293513A1 Method and system for design simplification through implication-based analysis
US2010269077A1 Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking