|
US2008244476A1
|
|
System and method for simultaneous optimization of multiple scenarios in an integrated circuit design
|
|
US2007204245A1
|
|
Method for accelerating the RC extraction in integrated circuit designs
|
|
US2007198960A1
|
|
Methods for tiling integrated circuit designs
|
|
US2006200266A1
|
|
Systems for performing parallel distributed processing for physical layout generation
|
|
US5440652A
|
|
Method and apparatus for preparing color separations based on n-way color relationships
|
|
US6147688A
|
|
Method and apparatus for defining and selectively repeating unit image cells
|
